Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 935

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.10.11 KTMSR—KT Modem Status Register (KT—D23:F3)
Address Offset: 06h
Default Value:
The functionality of the Modem is emulated by the FW. This register provides the status
of the current state of the control lines from the modem.
Bit
7
6
5
4
3
2
1
0
Datasheet
00h
Data Carrier Detect (DCD) — RO. In Loop Back mode this bit is connected by
hardware to the value of MCR bit 3.
Ring Indicator (RI) — RO. In Loop Back mode this bit is connected by hardware to
the value of MCR bit 2.
Data Set Ready (DSR) — RO. In Loop Back mode this bit is connected by hardware
to the value of MCR bit 0.
Clear To Send (CTS) — RO. In Loop Back mode this bit is connected by hardware to
the value of MCR bit 1.
Delta Data Carrier Detect (DDCD) — RO. This bit is set when bit 7 is changed.
This bit is cleared by hardware when the MSR register is being read by the HOST
driver.
Trailing Edge of Read Detector (TERI) — RO. This bit is set when bit 6 is changed
from 1 to 0. This bit is cleared by hardware when the MSR register is being read by
the Host driver.
Delta Data Set Ready (DDSR) — RO. This bit is set when bit 5 is changed. This bit
is cleared by hardware when the MSR register is being read by the Host driver.
Delta Clear To Send (DCTS) — RO. This bit is set when bit 4 is changed. This bit is
cleared by hardware when the MSR register is being read by the Host driver.
Attribute: RO
Size: 8 bits
Description
§ §
935