Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 899

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.5.15 CAPP—Capabilities List Pointer Register
(IDER—D22:F2)
Address Offset: 34h
Default Value:
Bit
7:0
23.5.16 INTR—Interrupt Information Register
(IDER—D22:F2)
Address Offset: 3C–3Dh Attribute:
Default Value:
Bit
15:8
7:0
23.5.17 PID—PCI Power Management Capability ID Register
(IDER—D22:F2)
Address Offset: C8–C9h
Default Value:
Bit
15:8
7:0
Datasheet
C8h
Capability Pointer (CP)— R/WO. This field indicates that the first capability pointer
is offset C8h (the power management capability).
0300h
Interrupt Pin (IPIN) — RO. A value of 1h/2h/3h/4h indicates that this function
implements legacy interrupt on INTA/INTB/INTC/INTD, respectively
FunctionValueINTx
(2 IDE)03hINTC
Interrupt Line (ILINE)— R/W. The value written in this register indicates which
input of the system interrupt controller, the device's interrupt pin is connected to.
This value is used by the OS and the device driver, and has no affect on the
hardware.
D001h
Next Capability (NEXT) — RO. Its value of D0h points to the MSI capability.
Cap ID (CID)— RO. This field indicates that this pointer is a PCI power management.
Attribute: RO
Size: 8 bits
Description
R/W, RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
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