Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 572

14.1.34 SATACR0—SATA Capability Register 0 (SATA–D31:F2)
Address Offset: A8h–ABh
Default Value:
Function Level Reset: No (Bits 15:8 only)
Note: This register is read-only 0 when SCC is 01h.
Bit
31:24 Reserved
Major Revision (MAJREV) — RO. Major revision number of the SATA Capability
23:20
Pointer implemented.
Minor Revision (MINREV) — RO. Minor revision number of the SATA Capability
19:16
Pointer implemented.
Next Capability Pointer (NEXT) — R/WO. Points to the next capability structure.
15:8
These bits are not reset by Function Level Reset.
Capability ID (CAP)— RO. This value of 12h has been assigned by the PCI SIG to
7:0
designate the SATA Capability Structure.
14.1.35 SATACR1—SATA Capability Register 1 (SATA–D31:F2)
Address Offset: ACh–AFh
Default Value:
Note: This register is read-only 0 when SCC is 01h.
Bit
31:16 Reserved
BAR Offset (BAROFST) — RO. Indicates the offset into the BAR where the Index/Data
pair are located (in Dword granularity). The Index and Data I/O registers are located at
offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h.
000h = 0h offset
001h = 4h offset
15:4
002h = 8h offset
003h = Bh offset
004h = 10h offset
...
FFFh = 3FFFh offset (max 16KB)
BAR Location (BARLOC) — RO. Indicates the absolute PCI Configuration Register
address of the BAR containing the Index/Data pair (in DWord granularity). The Index
and Data I/O registers reside within the space defined by LBAR in the SATA controller. A
value of 8h indicates offset 20h, which is LBAR.
0000 – 0011b = reserved
0100b = 10h => BAR0
3:0
0101b = 14h => BAR1
0110b = 18h => BAR2
0111b = 1Ch => BAR3
1000b = 20h => LBAR
1001b = 24h => BAR5
1010–1110b = reserved
1111b = Index/Data pair in PCI Configuration space. This is not supported in the PCH.
572
0010B012h
00000048h
SATA Controller Registers (D31:F2)
Attribute: RO, R/WO
Size: 32 bits
Description
Attribute: RO
Size: 32 bits
Description
Datasheet