Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 748

Bit
INTR — R/WC. This bit can only be set by termination of a command. INTR is not
dependent on the INTREN bit (offset SMB_BASE + 02h, bit 0) of the Host controller
register (offset 02h). It is only dependent on the termination of the command. If the
INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be
generated. Software can poll the INTR bit in this non-interrupt case.
1
0 = Software clears this bit by writing a 1 to it. The PCH then deasserts the interrupt or
1 = The source of the interrupt or SMI# was the successful completion of its last
HOST_BUSY — R/WC.
0 = Cleared by the PCH when the current transaction is completed.
1 = Indicates that the PCH is running a command from the host interface. No SMB
0
18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 02h
Default Value:
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
Bit
PEC_EN — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase
7 1 = Causes the host controller to perform the SMBus transaction with the Packet Error
START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status
6
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All
LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be
5
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h,
748
SMI#.
command.
registers should be accessed while this bit is set, except the BLOCK DATA BYTE
Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only
when the SMB_CMD bits in the Host Control Register are programmed for Block
2
command or I C Read command. This is necessary in order to check the DONE_STS
bit.
00h
appended.
Checking phase appended. For writes, the value of the PEC byte is transferred from
the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit
must be written prior to the write in which the START bit is set.
register (offset 00h) can be used to identify when the PCH has finished the
command.
registers should be setup prior to writing a 1 to this bit position.
received for the block. This causes the PCH to send a NACK (instead of an ACK)
after receiving the last byte.
bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is
set, the LAST_BYTE bit cannot be cleared. This prevents the PCH from running
some of the SMBus commands (Block Read/Write, I
SMBus Controller Registers (D31:F3)
Description
Attribute: R/W, WO
Size: 8-bits
Description
2
C Read, Block I
2
C Write).
Datasheet