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Intel Stratix 10 MX HBM2 IP User Manual

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Intel
Stratix
10 MX HBM2 IP User
Guide
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Updated for Intel
Quartus
Prime Design Suite: 17.1
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UG-20031 | December 2017
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Summary of Contents for Intel Stratix 10 MX HBM2 IP

  • Page 1 ® ® Intel Stratix 10 MX HBM2 IP User Guide ® ® Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe UG-20031 | December 2017 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    6.2 Intel Stratix 10 MX HBM2 IP Efficiency..............40 6.3 Intel Stratix 10 MX HBM2 IP Latency............... 42 6.4 Intel Stratix 10 MX HBM2 IP Timing.................42 7 Document Revision History for Intel Stratix 10 MX HBM2 IP User Guide......43 ® ®...

  • Page 3: Introduction To High Bandwidth Memory

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 4: Hbm2 Dram Structure

    Figure 2. High Bandwidth Memory Stack of Four DRAM Dies 1.3 Intel Stratix 10 MX HBM2 Features Intel Stratix 10 MX FPGAs offer the following HBM2 features. • Supports one to eight HBM2 channels per HBM2 interface in the Pseudo Channel mode.

  • Page 5: Intel Stratix 10 Mx Hbm2 Controller Features

    The full-rate user interface can operate at a frequency lower than the HBM2 interface frequency For information on supported clock frequencies, refer to Intel Stratix 10 MX HBM2 Supported Frequencies in Intel Stratix 10 MX HBM2 IP Controller Interface Signals.

  • Page 6: Intel Stratix 10 Mx Hbm2 Architecture

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 7 UG-20031 | December 2017 Figure 3. Block Diagram of Intel Stratix 10 MX HBM2 Implementation The user core clock drives the logic highlighted in green, while the UIB clocks the logic highlighted in blue. The UIB clock also drives the HBM2 interface clock. User logic can run up to one-to-four times slower than the HBM2 interface.
  • Page 8 Temperature output from HBM2. Cattrip Catastrophic temperature sensor. The Intel Stratix 10 MX HBM2 IP supports only the Pseudo Channel mode of the HBM2 specification. Pseudo Channel mode includes the following features: • Pseudo Channel mode divides a single HBM2 channel into two individual subchannels of 64 bit I/O.

  • Page 9: Intel Stratix 10 Mx Hbm2 Controller Architecture

    2 Intel Stratix 10 MX HBM2 Architecture UG-20031 | December 2017 Figure 4. Intel Stratix 10 MX HBM2 Interface Using HBM2 Channels 0 and 7 through the UIBSS There is one AXI interface per Pseudo Channel. The AXI4 protocol can handle concurrent writes and reads to the HBM2 controller.

  • Page 10: Intel Stratix 10 Mx Hbm2 Controller Details

    2 Intel Stratix 10 MX HBM2 Architecture UG-20031 | December 2017 Figure 5. Intel Stratix 10 MX HBM2 Controller Block Diagram 2.3.1 Intel Stratix 10 MX HBM2 Controller Details This topic explains some of the high level HBM2 controller features.
  • Page 11 2 Intel Stratix 10 MX HBM2 Architecture UG-20031 | December 2017 The user interface runs at full rate – that is, data provided on the AXI write or read data bus on each user clock cycle corresponds to that required in one HBM2 memory clock cycle.
  • Page 12 2 Intel Stratix 10 MX HBM2 Architecture UG-20031 | December 2017 Thermal Control The HBM2 controller uses the TEMP and CATTRIP outputs from the HBM2 device to manage temperature variations in the HBM2 interface. • Temperature compensated refresh (TEMP): The HBM2 DRAM provides temperature...
  • Page 13 2 Intel Stratix 10 MX HBM2 Architecture UG-20031 | December 2017 Power down enable To conserve power, the HBM2 controller can enter power-down mode when the bus is idle for a long time. You can select this option if required.

  • Page 14: Generating The Intel Stratix 10 Mx Hbm2 Ip

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 15: Parameterizing The Intel Stratix 10 Mx Hbm2 Ip

    Diagnostics • Example Designs 3.2 General Parameters for Intel Stratix 10 MX HBM2 IP The General tab allows you to select the channels that you want to implement, and to select the memory and fabric core clock frequency. Figure 7.
  • Page 16 3 Generating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Table 3. Group: General / FPGA Display Name Description Speed Grade Specifies the speed grade of the Intel Stratix 10 FPGA. HBM2 Device Type Select the HBM2 Memory Device: 4GB/4H refers to HBM2...

  • Page 17: Controller Parameters For Intel Stratix 10 Mx Hbm2 Ip

    Clock Signals on page 30 3.3 Controller Parameters for Intel Stratix 10 MX HBM2 IP The parameter editor contains one Controller tab for each memory channel that you specify on the General tab. The Controller tab allows you to select the HBM2 controller options that you want to enable.
  • Page 18 3 Generating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Table 7. Group: Controller/ Controller 0 Configuration Display Name Description Is clone of Specifies a controller from which to copy all parameter values; this parameter applies when you select more than one HBM2 controller.

  • Page 19: Diagnostic Parameters For Intel Stratix 10 Mx Hbm2 Ip

    Enables the write data mask (DM) input to the HBM2 DRAM. When you use the DM pins, you cannot use ECC. 3.4 Diagnostic Parameters for Intel Stratix 10 MX HBM2 IP The Diagnostics tab allows you to select traffic options and to enable the efficiency monitor that measures HBM2 controller efficiency during functional simulation.
  • Page 20 3 Generating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Figure 9. Diagnostics Tab – Enabling Default Traffic Pattern Figure 10. Diagnostics Tab – Enabling User-Configured Traffic Pattern Table 8. Group: Diagnostics / Traffic Generator Display Name...

  • Page 21: Example Designs Parameters For Intel Stratix 10 Mx Hbm2 Ip

    3.5 Example Designs Parameters for Intel Stratix 10 MX HBM2 IP The Example Designs tab allows you to configure example design files for simulation and synthesis.

  • Page 22: Generating The Example Design

    HBM2 DRAM for simulation. • qii - includes all the files required to compile the HBM2 IP example design in the Intel Quartus Prime software version 17.1. Timing closure will be supported in a future release. ®...

  • Page 23: Intel Stratix 10 Mx Hbm2 Ip Example Design For Synthesis

    3 Generating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Figure 12. Example Design Hierarchy 3.7 Intel Stratix 10 MX HBM2 IP Example Design for Synthesis The top level example design for synthesis is available under <Design Directory>/ . The hbm_0_example_design/qii/ed_synth/synth/ed_synth.v...
  • Page 24 3 Generating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Your user logic interfaces to the following signals through the top-level ed_synth.v module: • Clocks: — Reference clock input for the UIB PLL that generates the clocks for the UIBSS and the HBM2 DRA.

  • Page 25: Simulating The Intel Stratix 10 Mx Hbm2 Ip

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 26: Simulating Intel Stratix 10 Mx Hbm2 Ip With Modelsim

    The HBM2 Model is an abstract generic model representative of the HBM2 DRAM for simulation. This is not a vendor-specific model. 4.2 Simulating Intel Stratix 10 MX HBM2 IP with ModelSim* 1. Launch the ModelSim simulator. 2. Select File...

  • Page 27: Simulating Intel Stratix 10 Mx Hbm2 Ip With Synopsys Vcs

    Transcript window. do run.do 8. Upon completion of the simulation, the Transcript window displays efficiency data and other useful information. 4.3 Simulating Intel Stratix 10 MX HBM2 IP with Synopsys VCS* 1. Navigate to the project_directory/hbm_0_example_design/sim/ directory.
  • Page 28 4 Simulating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Figure 14. Controller Tab Settings for High Efficiency Simulation Figure 15. Diagnostics Tab Settings for High Efficiency Simulation ModelSim Navigate to the directory, open project_directory/sim/ed_sim/sim/mentor file in an editor, and change: msim_setup.tcl...
  • Page 29 4 Simulating the Intel Stratix 10 MX HBM2 IP UG-20031 | December 2017 Set TOP_LEVEL_NAME “altera_hbm_tg_axi_171.altera_hbm_tg_axi_tb” To simulate the design, follow the steps in Simulating HBM2 IP with ModelSim. Synopsys VCS Navigate to the project_directory/hbm_0_example_design/sim/ directory. Open the file in an editor, ed_sim/sim/synopsys/vcs vcs_setup.sh...

  • Page 30: Intel Stratix 10 Mx Hbm2 Ip Interface

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 31: Reset Signals

    The maximum user clock frequency describes the maximum clock frequency at which the core <-> UIB interface can run. The actual core clock frequency depends on the user interface requirements and timing closure in the Intel Quartus Prime Pro Edition software.

  • Page 32: Axi User-Interface Signals

    HBM-only reset, active high. Not supported in version 17.1. Related Links Intel Stratix 10 MX HBM2 IP Example Design for Synthesis on page 23 5.2.3 AXI User-interface Signals The user interface to the HBM2 controller follows the Amba AXI4 protocol specification.
  • Page 33 5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 Port Name Width Direction Description axi_0_0_awlen Input Burst Length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
  • Page 34 5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 Port Name Width Direction Description axi_0_0_wuser_strb Input Extra Write Strobes (AXI WUSER port). Indicates which byte lanes (for u0_wuser_data) hold valid data, signal is aligned to u0_wstrb. axi_0_0_wlast Input Write Last.
  • Page 35 5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 Port Name Width Direction Desription axi_0_0_arsize Input Burst Size. This signal indicates the size of each transfer in the burst. • 0b101 = 32 Bytes • 0b110 = 64 Bytes...

  • Page 36: User Axi Interface Timing

    5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 Related Links Intel Stratix 10 MX HBM2 IP Example Design for Synthesis on page 23 5.3 User AXI Interface Timing This section explains the interface timing details between user logic and the HBM2 controller.

  • Page 37: Axi Write Transaction

    5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 destination asserting the READY signal. Once the source asserts the VALID signal, it must remain asserted until the handshake occurs, at a rising clock edge at which VALID and READY are both high. Once the destination asserts READY, it can deassert READY before the source asserts VALID.

  • Page 38: Axi Read Transaction

    5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 AXI Write Data During a write burst, the master can assert the signal only when it drives WVALID valid write data. Once asserted, must remain asserted until the rising clock...
  • Page 39 5 Intel Stratix 10 MX HBM2 IP Interface UG-20031 | December 2017 Read Address The user logic asserts the signal only when it drives valid Read address ARVALID information. Once asserted, must remain asserted until the rising clock edge ARVALID after the HBM2 controller asserts the signal.

  • Page 40: Intel Stratix 10 Mx Hbm2 Ip Controller Performance

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 41 6 Intel Stratix 10 MX HBM2 IP Controller Performance UG-20031 | December 2017 • Write transactions – Refers to user write requests that the HBM2 controller accepts (user-asserted AXI WVALID and corresponding controller-asserted AXI WREADY). • Read transactions – Refers to user read requests that the HBM2 controller has processed (controller-asserted AXI RVALID and corresponding user-asserted AXI RREADY).

  • Page 42: Intel Stratix 10 Mx Hbm2 Ip Latency

    AXI core clock cycles seen during the simulation time. 6.4 Intel Stratix 10 MX HBM2 IP Timing The maximum HBM2 memory interface frequency is based on the Intel Stratix 10 MX device speed grade. The maximum core interface frequency is limited by the frequency at which the core logic can meet timing.

  • Page 43: Document Revision History For Intel Stratix 10 Mx Hbm2 Ip User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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