Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 593

SATA Controller Registers (D31:F2)
14.4.1.3 IS—Interrupt Status Register (D31:F2)
Address Offset: ABAR + 08h
Default Value:
This register indicates which of the ports within the controller have an interrupt pending
and require service.
Bit
31:6
5
4
3
2
1
0
Datasheet
0Bh
–
00000000h
Reserved. Returns 0.
Interrupt Pending Status Port[5] (IPS[5]) — R/WC.
0 = No interrupt pending.
1 = Port 5 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[4] (IPS[4]) — R/WC.
0 = No interrupt pending.
1 = Port 4 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[3] (IPS[3]) — R/WC.
0 = No interrupt pending.
1 = Port 3 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Interrupt Pending Status Port[2] (IPS[2]) — R/WC.
0 = No interrupt pending.
1 = Port 2 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Interrupt Pending Status Port[1] (IPS[1]) — R/WC.
0 = No interrupt pending.
1 = Port 1has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[0] (IPS[0]) — R/WC.
0 = No interrupt pending.
1 = Port 0 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Attribute: R/WC
Size: 32 bits
Description
593