Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 718

17.1.2.18 CORBWP—CORB Write Pointer Register
®
(Intel
Memory Address:HDBAR + 48h
Default Value:
Bit
15:8 Reserved.
CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this
field in DWord granularity. The DMA engine fetches commands from the CORB until the
7:0
Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1KB).
This register field may be written when the DMA engine is running.
17.1.2.19 CORBRP—CORB Read Pointer Register
®
(Intel
Memory Address:HDBAR + 4Ah
Default Value:
Bit
CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB
Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware
buffer within the Intel High Definition Audio controller. The hardware will physically
update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1
15
to verify that the reset completed correctly. Software must clear this bit back to 0 and
read back the 0 to verify that the clear completed correctly. The CORB DMA engine
must be stopped prior to resetting the Read Pointer or else DMA transfer may be
corrupted.
14:8 Reserved.
CORB Read Pointer (CORBRP)— RO. Software reads this field to determine how
many commands it can write to the CORB without over-running. The value read
indicates the CORB Read Pointer offset in DWord granularity. The offset entry read from
7:0
this field has been successfully fetched by the DMA controller and may be over-written
by software. Supports 256 CORB entries (256 x 4B=1KB). This field may be read while
the DMA engine is running.
718
High Definition Audio Controller—D27:F0)
0000h
High Definition Audio Controller—D27:F0)
0000h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
R/W
16 bits
R/W, RO
16 bits
Datasheet