Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 520

13.8.3.3 PM1_CNT—Power Management 1 Control
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
31:14
13
12:10
9:3
2
1
0
520
PMBASE + 04h
00000000h
No
Bits 0 7: Core,
–
Bits 8 12: RTC,
–
Bits 13 15: Resume
–
Reserved.
Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into
the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the
system should enter when the SLP_EN bit is set to 1. These bits are only reset by
RTCRST#.
Code Master Interrupt
000b ON: Typically maps to S0 state.
001b Puts Processor Core in S1 state.
010b Reserved
011b Reserved
100b Reserved
101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to
110b
S4 state.
Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to
111b
S5 state.
Reserved.
Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software
has a corresponding enable and status bits to control its ability to receive ACPI
events.
Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This
bit is reset to 0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enables Bus Master requests (internal or external) to cause a break from the C3
state.
If software fails to set this bit before going to C3 state, the PCH will still return to a
snoopable state from C3 or C4 states due to bus master activity.
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in
GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W, WO
Size: 32-bit
Usage: ACPI or Legacy
Description
Datasheet