Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 46

Introduction
AHCI
The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a
standardized programming interface for SATA host controllers. Platforms supporting
AHCI may take advantage of performance features such as no master/slave
designation for SATA devices—each device is treated as a master—and hardware-
assisted native command queuing. AHCI also provides usability enhancements such as
Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for
some features, hardware support in the SATA device or additional platform hardware.
Please see Section 1.3 for details on SKU feature availability.
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Intel Rapid Storage Technology
The PCH provides support for Intel Rapid Storage Technology, providing both AHCI (see
above for details on AHCI) and integrated RAID functionality. The RAID capability
provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of
the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined
on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID
features include hot spare support, SMART alerting, and RAID 0 auto replace. Software
components include an Option ROM for pre-boot configuration and boot functionality, a
Microsoft Windows* compatible driver, and a user interface for configuration and
management of the RAID capability of PCH. See Section 1.3 for details on SKU feature
availability.
PCI Interface
The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH
integrates a PCI arbiter that supports up to four external PCI bus masters in addition to
the internal PCH requests. This allows for combinations of up to four PCI down devices
and PCI slots. See Section 1.3 for details on SKU feature availability.
Low Pin Count (LPC) Interface
The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.
Serial Peripheral Interface (SPI)
The PCH implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required
to support Gigabit Ethernet and Intel Active Management Technology. The PCH
supports up to two SPI flash devices with speeds up to 50 MHz, using two chip select
pins.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-
byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
Channel 4 is reserved as a generic bus master request.
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Datasheet