Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 621

SATA Controller Registers (D31:F5)
15.1.6 PI—Programming Interface Register (SATA–D31:F5)
Address Offset: 09h
Default Value:
When SCC = 01h
Bit
7
6:4
3
2
1
0
15.1.7 SCC—Sub Class Code Register (SATA–D31:F5)
Address Offset: 0Ah
Default Value:
Bit
7:0
15.1.8 BCC—Base Class Code Register
(SATA–D31:F5SATA–D31:F5)
Address Offset: 0Bh
Default Value:
Bit
7:0
Datasheet
85h
This read-only bit is a 1 to indicate that the PCH supports bus master operation
Reserved.
Secondary Mode Native Capable (SNC) — RO. Indicates whether or not the
secondary channel has a fixed mode of operation.
0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 2.
This bit will always return 0.
Secondary Mode Native Enable (SNE) — RO.
Determines the mode that the secondary channel is operating in.
1 = Secondary controller operating in native PCI mode.
This bit will always return 1.
Primary Mode Native Capable (PNC) — RO. Indicates whether or not the primary
channel has a fixed mode of operation.
0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 0.
This bit will always return 0.
Primary Mode Native Enable (PNE) — RO.
Determines the mode that the primary channel is operating in.
1 = Primary controller operating in native PCI mode.
This bit will always return 1.
01h
Sub Class Code (SCC) — RO.
The value of this field determines whether the controller supports legacy IDE mode.
01h
Base Class Code (BCC) — RO.
01h = Mass storage device
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
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