Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 695

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Integrated Intel High Definition Audio Controller Registers
Bit
Power State (PS) — R/W. This field is used both to determine the current power state
of the Intel
00 = D0 state
11 = D3
Others = reserved
NOTES:
1:0
1. If software attempts to write a value of 01b or 10b in to this field, the write
2. When in the D3
3. When software changes this value from D3
17.1.1.26 MID—MSI Capability ID Register
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(Intel
Address Offset: 60h–61h
Default Value:
Bit
Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability
15:8
structure.
7:0 Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability.
17.1.1.27 MMC—MSI Message Control Register
®
(Intel
Address Offset: 62h–63h
Default Value:
Bit
15:8 Reserved
64b Address Capability (64ADD) — RO. Hardwired to 1. Indicates the ability to
7
generate a 64-bit message address.
Multiple Message Enable (MME) — RO. Normally this is a R/W register. However since
6:4
only 1 message is supported, these bits are hardwired to 000 = 1 message.
Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1
3:1
message.
MSI Enable (ME) — R/W.
0 0 = an MSI may not be generated
1 = an MSI will be generated instead of an INTx signal.
Datasheet
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High Definition Audio controller and to set a new power state.
state
HOT
operation must complete normally; however, the data is discarded and no state
change occurs.
states, the Intel
HOT
space is available, but the IO and memory space are not. Additionally, interrupts are
blocked.
warm (soft) reset is generated, and software must re-initialize the function.
High Definition Audio Controller—D27:F0)
7005h
High Definition Audio Controller—D27:F0)
0080h
Description
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High Definition Audio controller's configuration
state to the D0 state, an internal
HOT
Attribute: RO
Size: 16 bits
Description
Attribute: RO, R/W
Size: 16 bits
Description
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