Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 673

EHCI Controller Registers (D29:F0, D26:F0)
16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
Register
Offset:
Default Value:
This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the PCH host controller operates in 64-bit mode (as indicated by a 1 in
64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then
the most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be modified by
system software and will always return 0s when read. The memory structure
referenced by this physical memory pointer is assumed to be 32-byte aligned.
Bit
31:5
4:0
16.2.2.8 CONFIGFLAG—Configure Flag Register
Offset:
Default Value:
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset.
Bit
31:1
0
Datasheet
MEM_BASE + 38h–3Bh
00000000h
Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals
[31:5], respectively. This field may only reference a Queue Head (QH).
Reserved.
MEM_BASE + 60h–63h
00000000h
Reserved.
Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process
of configuring the Host controller. This bit controls the default port-routing control logic.
Bit values and side-effects are listed below. See Chapter 4 of the EHCI specification for
operation details.
0 = Compatibility debug only (default).
1 = Port routing control logic default-routes all ports to this host controller.
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
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