Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 369

Chipset Configuration Registers
10.1.13 V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 2020–2023h
Default Value:
Bit
31
30:28
27:24
23:16
15:10
9:8
7:1
0
10.1.14 V1STS—Virtual Channel 1 Resource Status Register
Offset Address: 2026–2027h
Default Value:
Bit
15:2
1
0
10.1.15 CIR31—Chipset Initialization Register 31
Offset Address: 2030–2033h
Default Value:
Bit
31:0
Datasheet
00000000h
Virtual Channel Enable (EN) — R/W. Enables the VC when set. Disables the VC
when cleared.
Reserved
Virtual Channel Identifier (ID) — R/W. Indicates the ID to use for this virtual
channel.
Reserved
Extended TC/VC Map (ETVM) — R/WL. Defines the upper 8-bits of the VC0 16-bit
TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic
class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/WL. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel. These bits are locked if the
TCLOCKDN bit (RCBA+0050h:bit 31) is set.
Reserved
0000h
Reserved
VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual
channel is still being negotiated with ingress ports.
Reserved
00000000h
CIR31 Field 0— R/WL. BIOS must set this field. These bits are locked if the
TCLOCKDN bit (RCBA+0050h:bit 31) is set.
Attribute: R/W, RO, R/WL
Size: 32-bit
Description
Attribute: RO
Size: 16-bit
Description
Attribute: R/WL, RO
Size: 32-bit
Description
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