Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 717

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Integrated Intel High Definition Audio Controller Registers
17.1.2.15 SSYNC—Stream Synchronization Register
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(Intel
Memory Address:HDBAR + 38h
Default Value:
Bit
31:8 Reserved
Stream Synchronization (SSYNC) — R/W. When set to 1, these bits block data from
being sent on or received from the link. Each bit controls the associated stream
descriptor (that is, bit 0 corresponds to the first stream descriptor, etc.)
To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits
for the associated stream descriptors are then set to 1 to start the DMA engines. When
all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at
the same time, and transmission or reception of bits to or from the link will begin
together at the start of the next full link frame.
To synchronously stop the streams, fist these bits are set, and then the individual RUN
bits in the stream descriptor are cleared by software.
7:0
If synchronization is not desired, these bits may be left as 0, and the stream will simply
begin running normally when the stream's RUN bit is set.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
17.1.2.16 CORBLBASE—CORB Lower Base Address Register
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(Intel
Memory Address:HDBAR + 40h
Default Value:
Bit
CORB Lower Base Address — R/W. Lower address of the Command Output Ring
Buffer, allowing the CORB base address to be assigned on any 128-B boundary. This
31:7
register field must not be written when the DMA engine is running or the DMA transfer
may be corrupted.
CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the
6:0
CORB to be allocated with 128B granularity to allow for cache line fetch optimizations.
17.1.2.17 CORBUBASE—CORB Upper Base Address Register
®
(Intel
Memory Address:HDBAR + 44h
Default Value:
Bit
CORB Upper Base Address — R/W. Upper 32 bits of the address of the Command
31:0 Output Ring buffer. This register field must not be written when the DMA engine is
running or the DMA transfer may be corrupted.
Datasheet
High Definition Audio Controller—D27:F0)
00000000h
High Definition Audio Controller—D27:F0)
00000000h
High Definition Audio Controller—D27:F0)
00000000h
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
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