Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 902

23.5.21 MC—Message Signaled Interrupt Message Control
Register (IDER—D22:F2)
Address Offset: D2–D3h
Default Value:
Bit
15:8
7
6:4
3:1
0
23.5.22 MA—Message Signaled Interrupt Message Address
Register (IDER—D22:F2)
Address Offset: D4–D7h
Default Value:
Bit
31:2
1:0
23.5.23 MAU—Message Signaled Interrupt Message Upper
Address Register (IDER—D22:F2)
Address Offset: D8–DBh
Default Value:
Bit
31:4
3:0
23.5.24 MD—Message Signaled Interrupt Message Data
Register (IDER—D22:F2)
Address Offset: DC–DDh
Default Value:
Bit
15:0
902
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
0080h
Reserved
64 Bit Address Capable (C64) — RO. Capable of generating 64-bit and 32-bit
messages.
Multiple Message Enable (MME) — R/W. These bits are R/W for software
compatibility, but only one message is ever sent by the PT function.
Multiple Message Capable (MMC) — RO. Only one message is required.
MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are
not used to generate interrupts.
00000000h
Address (ADDR) — R/W. This field contains the Lower 32 bits of the system
specified message address, always DWord aligned
Reserved
00000000h
Reserved
Address (ADDR) — R/W. This field contains the Upper 4 bits of the system specified
message address.
0000h
Data (DATA) — R/W. This content is driven onto the lower word of the data bus of
the MSI memory write transaction.
Attribute: RO, R/W
Size: 16 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: RO, R/W
Size: 32 bits
Description
Attribute: R/W
Size: 16 bits
Description
Datasheet