Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 776

19.1.29 LCTL—Link Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 50h–51h
Default Value:
Bit
15:10 Reserved
Hardware Autonomous Width Disable – RO. Hardware never attempts to change
9
the link width except when attempting to correct unreliable Link operation.
8 Reserved
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
7
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
Common Clock Configuration (CCC) — R/W.
6
0 = The PCH and device are not using a common reference clock.
1 = The PCH and device are operating with a distributed common reference clock.
Retrain Link (RL) — R/W.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5/F6/F7:52, bit 11) to check the
5
NOTE: It is permitted to write 1b to this bit while simultaneously writing modified
Link Disable (LD) — R/W.
4
0 = Link enabled.
1 = The root port will disable the link.
Read Completion Boundary Control (RCBC) — RO. Indicates the read completion
3
boundary is 64 bytes.
2 Reserved
Active State Link PM Control (APMC) — R/W. Indicates whether the root port should
enter L0s or L1 or both.
00 = Disabled
1:0
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled
776
0000h
L1 prior to entering L0.
status of training.
values to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the
LTSSM is already in Recovery or Configuration, the modified values are not
required to affect the Link training that is already in progress.
PCI Express* Configuration Registers
Attribute: R/W, RO
Size: 16 bits
Description
Datasheet