Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 98

Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 4 of 6)
Signal Name
CLKOUT_ITPXDP_P
CLKOUT_ITPXDP_N
CLKOUT_DP_P
CLKOUT_DP_N
CLKOUT_DMI_P,
CLKOUT_DMI_N
CLKOUT_PEG_A_P,
CLKOUT_PEG_A_N
CLKOUT_PEG_B_P,
CLKOUT_PEG_B_N
CLKOUT_PCIE[7:0]P,
CLKOUT_PCIE[7:0]N
CLKOUT_PCI[4:0]
CLKOUTFLEX[3:0]/
GPIO[67:64]
XTAL25_OUT
XCLK_RCOMP
HDA_RST#
7
HDA_SDO
7
HDA_SYNC
13
HDA_BCLK
7
GPIO8
7
GPIO15
7
GPIO27 (Non-Deep S4/
S5 mode)
7
GPIO27 (Deep S4/S5
mode)
12
GPIO28
GPIO32
GPIO57
9
GPIO72
GPIO0
9
GPIO13
9
GPIO30
98
Power During
1
Plane Reset
Clocking Signals
Core Running
Core Running
Core Running
Core Running
Core Running
Core Running
Core Running
Core Low
Core Running
Core High-Z
®
Intel High Definition Audio Interface
Suspend Low
Suspend Low
Suspend Low
Suspend Low
UnMultiplexed GPIO Signals
Suspend High
Suspend Low
DSW High-Z
DSW High-Z
Suspend High
Core High
Suspend Low
Suspend High
Multiplexed GPIO Signals used as GPIO only
Core High-Z (Input)
Suspend High-Z
Suspend High-Z (Input)
Immediately
S0/S1
1
after Reset
Running Running
Running Running
Running Running
Running Running
Running Running
Running Running
Running Running
Running Running
Running Running
High-Z High-Z
3
Low Defined
Low Defined
Low Defined
Low Low
High Defined
Low Defined
High-Z High-Z
High-Z High-Z
Low Low
High Defined
High-Z (Input) Defined
High Defined
High-Z (Input) Defined
High-Z High-Z
High-Z (Input) Defined
PCH Pin States
S3 S4/S5
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Low Low
Low Low
Low Low
Low Low
Defined Defined
Defined Defined
High-Z High-Z
High-Z High-Z
Low Low
Off Off
Defined Defined
Defined Defined
Off Off
High-Z High-Z
Defined Defined
Datasheet