Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 463

LPC Interface Bridge Registers (D31:F0)
13.1.26 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0)
Offset Address: 90h
Default Value:
Bit
31:24
23:18
17:16
15:2
1
0
13.1.27 ULKMC — USB Legacy Keyboard / Mouse Control
(LPC I/F—D31:F0)
Offset Address: 94h
Default Value:
Bit
31:16
15
14:12
11
Datasheet
93h
–
00000000h
Reserved
Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
Reserved
Generic I/O Decode Range 4 Base Address (GEN4_BASE) — R/W.
NOTE: The PCH Does not provide decode down to the word or byte level
Reserved
Generic Decode Range 4 Enable (GEN4_EN) — R/W.
0 = Disable.
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
97h
–
00002000h
Reserved
SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if
the event occurred. Note that even if the corresponding enable bit is not set in bit 7,
then this bit will still be active. It is up to the SMM code to use the enable bit to
determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred
Reserved
SMI Caused by Port 64 Write (TRAPBY64W) — R/WC. This bit indicates if the
event occurred. Note that even if the corresponding enable bit is not set in bit 3, this
bit will still be active. It is up to the SMM code to use the enable bit to determine the
exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific
port 64h writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
Attribute: R/W
Size: 32 bit
Power Well: Core
Description
Attribute: RO, R/WC, R/W
Size: 32 bit
Power Well: Core
Description
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