Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 911

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.6.17 IDEDHIR—IDE Drive/Head In Register
(IDER—D22:F2)
Address Offset: 06h
Default Value:
This register implements the Drive/Head register of the command block of the IDE.
This register can be written only by the Host. When host writes to this register, all 3
registers (IDEDHIR, IDEDHOR0, IDEDHOR1) are updated with the written value.
Host read to this register address reads the IDE Drive/Head Out Register (IDEDHOR0)
if DEV=0 or IDEDHOR1 if DEV=1.
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to '1') in addition to Host system reset and D3->D0
transition of the function.
Bit
7:0
23.6.18 IDDHOR1—IDE Drive Head Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 06h
Default Value:
This register is read only by the Host. Host read to this Drive/head In register address
reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=1
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to '1') in addition to the Host system reset and D3
to D0 transition of the IDE function.
When the host writes to this address, it updates the value of the IDEDHIR register.
Bit
7:0
Datasheet
00h
IDE Drive/Head Data (IDEDHD) — R/W. Register defines the drive number, head
number and addressing mode.
00h
IDE Drive Head Out DEV 1 (IDEDHO1) — R/W. Drive/Head Out register of Slave
device.
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
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