Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 123

Functional Description
The integrated GbE controller provides a system interface using a PCI Express function.
A full memory-mapped or I/O-mapped interface is provided to the software, along with
DMA mechanisms for high performance data transfer.
The integrated GbE controller features are:
• Network Features
— Compliant with the 1 Gb/s Ethernet 802.3 802.3u 802.3ab specifications
— Multi-speed operation: 10/100/1000 Mb/s
— Full-duplex operation at 10/100/1000 Mb/s: Half-duplex at 10/100 Mb/s
— Flow control support compliant with the 802.3X specification
— VLAN support compliant with the 802.3q specification
— MAC address filters: perfect match unicast filters; multicast hash filtering,
broadcast filter and promiscuous mode
— PCI Express/SMBus interface to GbE PHYs
• Host Interface Features
— 64-bit address master support for systems using more than 4 GB of physical
memory
— Programmable host memory receive buffers (256 Bytes to 16 KB)
— Intelligent interrupt generation features to enhance driver performance
— Descriptor ring management hardware for transmit and receive
— Software controlled reset (resets everything except the configuration space)
— Message Signaled Interrupts
• Performance Features
— Configurable receive and transmit data FIFO, programmable in 1 KB increments
— TCP segmentation capability compatible with Windows NT* 5.x off loading
features
— Fragmented UDP checksum offload for packet reassembly
— IPv4 and IPv6 checksum offload support (receive, transmit, and TCP
segmentation offload)
— Split header support to eliminate payload copy from user space to host space
— Receive Side Scaling (RSS) with two hardware receive queues
— Supports 9018 bytes of jumbo packets
— Packet buffer size
— LinkSec offload compliant with 802.3ae specification
— TimeSync offload compliant with 802.1as specification
• Virtualization Technology Features
— Warm function reset – function level reset (FLR)
— VMDq1
• Power Management Features
— Magic Packet* wake-up enable with unique MAC address
— ACPI register set and power down functionality supporting D0 and D3 states
— Full wake up support (APM, ACPI)
— MAC power down at Sx, DMoff with and without WoL
Datasheet 123