Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 453

LPC Interface Bridge Registers (D31:F0)
13.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h
Default Value:
Lockable:
Bit
7
6:3
2:0
13.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F —
D31:F0)
Offset Address: 48h–4Bh
Default Value:
Bit
31:16
15:7
6:1
0
Datasheet
00h
No
ACPI Enable (ACPI_EN) — R/W.
0 = Disable.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the
ACPI power management function is enabled. Note that the APM power
management ranges (B2/B3h) are always enabled and are not affected by this bit.
Reserved
SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI
must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream,
but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ20–23, and can be shared with other interrupts.
Bits SCI Map
000b IRQ9
001b IRQ10
010b IRQ11
011b Reserved
IRQ20 (Only available if APIC
100b
enabled)
IRQ21 (Only available if APIC
101b
enabled)
When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be
programmed for active-high reception. When the interrupt is mapped to APIC interrupts
20 through 23, the APIC should be programmed for active-low reception.
00000001h
Reserved. Always 0.
Base Address (BA) — R/W. Provides the 128 bytes of I/O space for GPIO.
Reserved. Always 0.
RO. Hardwired to 1 to indicate I/O space.
Attribute: R/W
Size: 8 bit
Usage: ACPI, Legacy
Power Well: Core
Description
Attribute: R/W, RO
Size: 32 bit
Description
453