Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 564

Hide thumbs Also See for 6 SERIES CHIPSET - DATASHEET 01-2011:
Table of Contents

Advertisement

14.1.26
MSICI—Message Signaled Interrupt Capability
Identification (SATA–D31:F2)
Address Offset: 80h
Default Value:
Note:
There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits
Next Pointer (NEXT) — RO. Indicates the next item in the list is the PCI power
15:8
management pointer.
7:0
Capability ID (CID) — RO. Capabilities ID indicates MSI.
14.1.27
MSIMC—Message Signaled Interrupt Message Control
(SATA–D31:F2)
Address Offset: 82h
Default Value:
Note:
There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits
15:8
Reserved
7
64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.
564
81h
7005h
83h
0000h
SATA Controller Registers (D31:F2)
Attribute:
RO
Size:
16 bits
Description
Attribute:
R/W, RO
Size:
16 bits
Description
Datasheet

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

6 series

Table of Contents