Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 383

Chipset Configuration Registers
10.1.34 D27IP—Device 27 Interrupt Pin Register
Offset Address: 3110–3113h
Default Value:
Bit
31:4
3:0
10.1.35 D26IP—Device 26 Interrupt Pin Register
Offset Address: 3114–3117h
Default Value:
Bit
31:4
3:0
10.1.36 D25IP—Device 25 Interrupt Pin Register
Offset Address: 3118–311Bh
Default Value:
Bit
31:4
3:0
Datasheet
00000001h
Reserved
®
Intel High Definition Audio Pin (ZIP) — R/W. Indicates which pin the Intel
High Definition Audio controller drives as its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
30000321h
Reserved
EHCI #2 Pin (E2P) — R/W. Indicates which pin EHCI controller #2 drives as its
interrupt, if controller exists.
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserve
NOTE: EHCI Controller #2 is mapped to Device 26 Function 0.
00000001h
Reserved
GbE LAN Pin (LIP) — R/W. Indicates which pin the internal GbE LAN controller
drives as its interrupt
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
®
383