Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 565

SATA Controller Registers (D31:F2)
Bits
Multiple Message Enable (MME) — RO.
= 000 (and MSIE is set), a single MSI message will be generated for all SATA ports, and
bits [15:0] of the message vector will be driven from MD[15:0].
6:4
All other MME values are reserved. If this field is set to one of these reserved values, the
results are undefined.
NOTE: The CCC interrupt is generated on unimplemented port (AHCI PI register bit
3:1 Multiple Message Capable (MMC) — RO. MMC is not supported.
MSI Enable (MSIE) — R/W /RO. If set, MSI is enabled and traditional interrupt pins
are not used to generate interrupts. This bit is R/W when SC.SCC is not 01h and is read-
only 0 when SCC is 01h. Note that CMD.ID bit has no effect on MSI.
0
NOTE: Software must clear this bit to 0 to disable MSI first before changing the number
Datasheet
For 6 port components:
Value Driven on MSI Memory Write
MME
Bits[15:3]
000,
MD[15:3]
001, 010
011 MD[15:3]
For 4 port components:
Value Driven on MSI Memory Write
MME
Bits[15:3]
000,
MD[15:3]
001, 010
011 MD[15:3]
equal to 0). If CCC interrupt is disabled, no MSI shall be generated for the port
dedicated to the CCC interrupt. When CCC interrupt occurs, MD[2:0] is
dependant on CCC_CTL.INT (in addition to MME).
of messages allocated in the MMC field. Software must also make sure this bit is
cleared to '0' when operating in legacy mode (when GHC.AE = 0).
Description
Bit[2] Bit[1]
MD[2] MD[1]
Port 0: 0 Port 0: 0
Port 1: 0 Port 1: 0
Port 2: 0 Port 2: 1
Port 3: 0 Port 3: 1
Port 4: 1 Port 4: 0
Port 5: 1 Port 5: 0
Bit[2] Bit[1]
MD[2] MD[1]
Port 0: 0 Port 0: 0
Port 1: 0 Port 1: 0
Port 4: 1 Port 2: 0
Port 5: 1 Port 3: 0
Bit[0]
MD[0]
Port 0: 0
Port 1: 1
Port 2: 0
Port 3: 1
Port 4: 0
Port 5: 1
Bit[0]
MD[0]
Port 0: 0
Port 1: 1
Port 2: 0
Port 3: 1
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