Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 426

Bit
VGA Enable (VGAE) — R/W. When set to a 1, the PCH PCI bridge forwards the
following transactions to PCI regardless of the value of the I/O base and limit registers.
The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE
(D30:F0:04 bit 0) being set.
3
The same holds true from secondary accesses to the primary interface in reverse. That
is, when the bit is 0, memory and I/O addresses on the secondary interface between
the above ranges will be claimed.
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is
2
set, the PCH PCI bridge will block any forwarding from primary to secondary of I/O
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).
SERR# Enable (SEE) — R/W. Controls the forwarding of secondary interface SERR#
assertions on the primary interface. When set, the PCI bridge will forward SERR# pin.
1
Parity Error Response Enable (PERE) — R/W.
0 = Disable
0
1 = The PCH PCI bridge is enabled for parity error reporting based on parity errors on
426
• Memory addresses: 000A0000h–000BFFFFh
• I/O addresses: 3B0h–3BBh and 3C0h–3DFh. For the I/O addresses, bits [63:16] of the address
must be 0, and bits [15:10] of the address are ignored (that is, aliased).
• SERR# is asserted on the secondary interface.
• This bit is set.
• CMD.SEE (D30:F0:04 bit 8) is set.
the PCI bus.
PCI-to-PCI Bridge Registers (D30:F0)
Description
Datasheet