Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 702

17.1.1.42 VC0CTL—VC0 Resource Control Register
®
(Intel
Address Offset: 114h–117h
Default Value:
Function Level Reset: No
Bit
31 VC0 Enable — RO. Hardwired to 1 for VC0.
30:27 Reserved.
26:24 VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0.
23:20 Reserved.
Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint
19:17
devices.
Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint
16
devices.
15:8 Reserved.
TC/VC0 Map — R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits
7:0
[7:1] are implemented as R/W bits.
17.1.1.43 VC0STS—VC0 Resource Status Register
®
(Intel
Address Offset: 11Ah–11Bh
Default Value:
Bit
15:2 Reserved.
VC0 Negotiation Pending — RO. Hardwired to 0 since this bit does not apply to the
1
integrated Intel
Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for
0
endpoint devices.
702
High Definition Audio Controller—D27:F0)
800000FFh
High Definition Audio Controller—D27:F0)
0000h
®
High Definition Audio device.
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
R/W, RO
32 bits
RO
16 bits
Datasheet