Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 650

16.1.20 PWR_CNTL_STS—Power Management Control/
Status Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 54h
Default Value:
Function Level Reset: No (Bits 8 and 15 only)
Bit
PME Status — R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if
1 = This bit is set when the PCH EHC would normally assert the PME# signal
15
NOTE: This bit must be explicitly cleared by the operating system each time the
This bit is not reset by Function Level Reset.
Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data
14:13
register.
Data Select — RO. Hardwired to 0000b indicating it does not support the associated
12:9
Data register.
PME Enable — R/W.
0 = Disable.
1 = Enables the PCH EHC to generate an internal PME signal when PME_Status is 1.
8
NOTE: This bit must be explicitly cleared by the operating system each time it is
This bit is not reset by Function Level Reset.
7:2 Reserved
Power State — R/W. This 2-bit field is used both to determine the current power state
of EHC function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3
If software attempts to write a value of 10b or 01b in to this field, the write operation
must complete normally; however, the data is discarded and no state change occurs.
1:0
When in the D3
but the configuration space must still be accessible. When not in the D0 state, the
generation of the interrupt output is blocked. Specifically, the PIRQH is not asserted by
the PCH when not in the D0 state.
When software changes this value from the D3
warm (soft) reset is generated, and software must re-initialize the function.
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
650
55h
–
0000h
enabled).
independent of the state of the PME_En bit.
operating system is loaded.
initially loaded.
state
HOT
state, the PCH must not accept accesses to the EHC memory range;
HOT
EHCI Controller Registers (D29:F0, D26:F0)
Attribute: R/W, R/WC, RO
Size: 16 bits
Description
state to the D0 state, an internal
HOT
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