Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 807

High Precision Event Timer Registers
20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message
Interrupt Rout Register
Address Offset: Timer 0:
Default Value:
Note: The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7.
Software can access the various bytes in this register using 32-bit or 64-bit accesses.
32-bit accesses can be done to offset 1x0h or 1x4h. 64-bit accesses can be done to
1x0h. 32-bit accesses must not be done to offsets 1x1h, 1x2h, 1x3h, 1x5h, 1x6h, or
1x7h.
Bit
63:32
31:0
Datasheet
110–117h,
Timer 1: 130–137h,
Timer 2: 150–157h,
Timer 3: 170–177h,
Timer 4: 190–197h,
Timer 5: 1B0–1B7h,
Timer 6: 1D0–1D7h,
Timer 7: 1F0–1F7h,
N/A
Tn_PROCMSG_INT_ADDR — R/W. Software sets this 32-bit field to indicate the
location that the direct processor interrupt message should be written.
Tn_PROCMSG_INT_VAL — R/W. Software sets this 32-bit field to indicate that
value that is written during the direct processor interrupt message.
Attribute: R/W
Size: 64 bit
Description
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