Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 90

Table 2-27. Functional Strap Definitions (Sheet 4 of 5)
Signal
DF_TVS
GPIO28
HDA_SYNC
GPIO15
L_DDC_DATA
SDVO_CTRLDATA
DDPC_CTRLDATA
DDPD_CTRLDATA
DSWVRMEN
90
When
Usage
Sampled
DMI and FDI Tx/
Rising edge
Rx Termination
of PWROK
Voltage
On-Die PLL
Rising edge of
Voltage
RSMRST# pin
Regulator
On-Die PLL
Voltage Rising edge of
Regulator RSMRST# pin
Voltage Select
TLS Rising edge of
Confidentiality RSMRST# pin
Rising edge of
LVDS Detected
PWROK
Rising edge of
Port B Detected
PWROK
Rising edge of
Port C Detected
PWROK
Rising edge of
Port D Detected
PWROK
Deep S4/S5 Well
On-Die Voltage Always
Regulator Enable
Comment
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
This signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
RSMRST# deasserts.
The On-Die PLL voltage regulator is enabled
when sampled high. When sampled low the On-
Die PLL Voltage Regulator is disabled.
This signal has a weak internal pull-down.
On Die PLL VR is supplied by 1.5 V from VccVRM
when sampled high, 1.8 V from VccVRM when
sampled low.
Low = Intel ME Crypto Transport Layer Security
(TLS) cipher suite with no confidentiality
High = Intel ME Crypto TLS cipher suite with
confidentiality
This signal has a weak internal pull-down.
NOTES:
1. The weak internal pull-down is disabled
after RSMRST# deasserts.
2. A strong pull-up may be needed for GPIO
functionality
3. This signal must be pulled up to support
Intel AMT with TLS. Intel ME
configuration parameters also need to be
set correctly to enable TLS.
When '1'- LVDS is detected; When '0'- LVDS is
not detected.
NOTE: This signal has a weak internal pull-
down. The internal pull-down is disabled
after PLTRST# deasserts.
When '1'- Port B is detected; When '0'- Port B is
not detected
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
When '1'- Port C is detected; When '0'- Port C is
not detected
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
When '1'- Port D is detected; When '0'- Port D is
not detected
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
If strap is sampled high, the Integrated Deep
S4/S5 Well (DSW) On-Die VR mode is enabled.
Signal Description
Datasheet