Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 441

Gigabit LAN Configuration Registers
12.1.20 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0)
Address Offset: CAh
Default Value:
Function Level Reset: No (Bits 15:11 only)
Bit
15:11
10
9
8:6
5
4
3
2:0
Datasheet
CBh
–
See bit descriptions
PME_Support (PMES) — RO. This five-bit field indicates the power states in which the
function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the
NVM:
Condition
PM Ena=0
PM Ena & AUX-PWR=0
PM Ena & AUX-PWR=1
These bits are not reset by Function Level Reset.
D2_Support (D2S) — RO. The D2 state is not supported.
D1_Support (D1S) — RO. The D1 state is not supported.
Aux_Current (AC) — RO. Required current defined in the Data Register.
Device Specific Initialization (DSI) — RO. Set to 1. The GbE LAN Controller requires
its device driver to be executed following transition to the D0 un-initialized state.
Reserved
PME Clock (PMEC) — RO. Hardwired to 0.
Version (VS) — RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI
Power Management Specification.
Attribute:
Size:
Description
Function
No PME at all states
PME at D0 and D3hot
PME at D0, D3hot and
D3cold
RO
16 bits
Value
0000b
01001b
11001b
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