Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 578

14.1.43 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset: E4h
Default Value:
Bits
BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form
the contents of the second DWord of any BIST FIS initiated by the PCH. This register is
not port specific—its contents will be used for BIST FIS initiated on any port. Although
31:0 the 2nd and 3rd DWs of the BIST FIS are only meaningful when the "T" bit of the BIST
FIS is set to indicate "Far-End Transmit mode", this register's contents will be
transmitted as the BIST FIS 2nd DW regardless of whether or not the "T" bit is indicated
in the BFCS register (D31:F2:E0h).
14.1.44 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h
Default Value:
Bits
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form
the contents of the third DWord of any BIST FIS initiated by the PCH. This register is not
port specific—its contents will be used for BIST FIS initiated on any port. Although the
31:0 2nd and 3rd DWs of the BIST FIS are only meaningful when the "T" bit of the BIST FIS
is set to indicate "Far-End Transmit mode", this register's contents will be transmitted as
the BIST FIS 3rd DW regardless of whether or not the "T" bit is indicated in the BFCS
register (D31:F2:E0h).
578
E7h
–
00000000h
EBh
–
00000000h
SATA Controller Registers (D31:F2)
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Datasheet