Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 573

SATA Controller Registers (D31:F2)
14.1.36 FLRCID—FLR Capability ID (SATA–D31:F2)
Address Offset: B0–B1h
Default Value:
Bit
15:8 Next Capability Pointer — RO. 00h indicates the final item in the capability list.
Capability ID — RO. The value of this field depends on the FLRCSSEL
(RCBA+3410h:bit 12) bit.
7:0
14.1.37 FLRCLV—FLR Capability Length and Version (SATA–
D31:F2)
Address Offset: B2–B3h
Default Value:
Function Level Reset: No (Bit 9:8 Only when FLRCSSEL = 0)
When FLRCSSEL (RCBA+3410h:bit 12) = 0, this register is defined as follows:
Bit
15:10 Reserved.
FLR Capability — R/WO.
1 = Support for Function Level reset.
9
This bit is not reset by the Function Level Reset.
TXP Capability — R/WO.
8 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is
Vendor-Specific Capability ID — RO. This field indicates the number of bytes of this
7:0 Vendor Specific capability as required by the PCI specification. It has the value of 06h
for the FLR capability.
When FLRCSSEL = 1, this register is defined as follows:
Bit
Vendor-Specific Capability ID — RO. A value of 2h identifies this capability as the
15:12
Function Level Reset (FLR).
11:8 Capability Version — RO. This field indicates the version of the FLR capability.
Vendor-Specific Capability ID — RO. This field indicates the number of bytes of this
7:0 Vendor Specific capability as required by the PCI specification. It has the value of 06h
for the FLR capability.
Datasheet
0009h
FLRCSSEL
(RCBA+3410h:bit 12) Value
0b
1b
xx06h
supported.
Attribute:
Size:
Description
Capability ID
Register Value
13h
09h (Vendor Specific)
Attribute:
Size:
Description
Description
RO
16 bits
RO, R/WO
16 bits
573