Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 730

17.1.2.41 SDFIFOS—Stream Descriptor FIFO Size Register – Input Streams
®
(Intel
Memory Address:Input Stream[0]: HDBAR + 90h
Default Value:
Bit
FIFO Size —R/W. Indicates the maximum number of bytes that could be evicted by the
controller at one time. This is the maximum number of bytes that may have been
received from the link but not yet DMA'd into memory, and is also the maximum
possible value that the PICB count will increase by at one time.
15:0
The FIFO size is calculated based on factors including the stream format programmed
in SDFMT register. As the default value is zero, SW must write to the respective SDFMT
register to kick of the FIFO size calculation, and read back to find out the HW allocated
FIFO size.
17.1.2.42 SDFIFOS—Stream Descriptor FIFO Size Register – Output Streams
®
(Intel
Memory Address:Output Stream[0]: HDBAR + 110h
Default Value:
Bit
FIFO Size — R/W. Indicates the maximum number of bytes that could be fetched by
the controller at one time. This is the maximum number of bytes that may have been
DMA'd into memory but not yet transmitted on the link, and is also the maximum
possible value that the PICB count will increase by at one time.
15:0
The FIFO size is calculated based on factors including the stream format programmed
in SDFMT register. As the default value is zero, SW must write to the respective SDFMT
register to kick of the FIFO size calculation, and read back to find out the HW allocated
FIFO size.
730
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + B0h
Input Stream[2]: HDBAR + D0h
Input Stream[3]: HDBAR + F0h
0000h
High Definition Audio Controller—D27:F0)
Output Stream[1]: HDBAR + 130h
Output Stream[2]: HDBAR + 150h
Output Stream[3]: HDBAR + 170h
0000h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:16 bits
Description
Attribute: R/W
Description
RO
Size: 16 bits
Datasheet