Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 703

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Integrated Intel High Definition Audio Controller Registers
17.1.1.44 VCiCAP—VCi Resource Capability Register
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(Intel
Address Offset: 11Ch–11Fh
Default Value:
Bit
Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for
31:24
endpoint devices.
23 Reserved.
Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint
22:16
devices.
Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint
15
devices.
Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for
14
endpoint devices.
13:8 Reserved
Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint
7:0
devices.
17.1.1.45 VCiCTL—VCi Resource Control Register
®
(Intel
Address Offset: 120h–123h
Default Value:
Function Level Reset: No
Bit
VCi Enable — R/W.
0 = VCi is disabled
31
1 = VCi is enabled
NOTE: This bit is not reset on D3
30:27 Reserved.
VCi ID — R/W. This field assigns a VC ID to the VCi resource. This field is not used by
26:24
the PCH hardware, but it is R/W to avoid confusing software.
23:20 Reserved.
Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint
19:17
devices.
Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint
16
devices.
15:8 Reserved.
TC/VCi Map — R/W, RO. This field indicates the TCs that are mapped to the VCi
resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1]
7:0
are implemented as R/W bits. This field is not used by the PCH hardware, but it is R/W
to avoid confusing software.
Datasheet
High Definition Audio Controller—D27:F0)
00000000h
High Definition Audio Controller—D27:F0)
00000000h
Attribute:
Size:
Description
Attribute:
Size:
Description
to D0 transition; however, it is reset by PLTRST#.
HOT
RO
32 bits
R/W, RO
32 bits
703