Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 109

PCH Pin States
Table 3-4. Power Plane for Input Signals for Desktop Configurations (Sheet 3 of 3)
Signal Name
2
INTVRMEN
RTCRST#
SRTCRST#
DDP[B:C:D]_HPD
SDVO_INTP,
SDVO_INTN
SDVO_TVCLKINP,
SDVO_TVCLKINN
SDVO_STALLP,
SDVO_STALLN
FDI_RXP[7:0],
FDI_RXN[7:0]
CLKIN_SATA_N,
CLKIN_SATA_P
CLKIN_DOT_96P,
CLKIN_DOT_96N
CLKIN_DMI_P,
CLKIN_DMI_N
CLKIN_PCILOOPBACK
PCIECLKRQ[7:5]#/
1
GPIO[46:44]
1
PCIECLKRQ2#/GPIO20
REFCLK14IN
XTAL25_IN
SPI_MISO
NOTE:
1. These signals can be configured as outputs in GPIO mode.
2. This signal is sampled as a functional strap during Reset. Refer to Functional straps
definition table for usage.
3. External termination is also required for JTAG enabling.
4. Not all signals or pin functionalities may be available on a given SKU. See
Chapter 2
Datasheet
Power Well Driver During Reset
Miscellaneous Signals
RTC External Pull-up
RTC External RC Circuit
RTC External RC Circuit
Digital Display Interface
Core External Pull-down
Core SDVO controller device
Core SDVO controller device
Core SDVO controller device
®
Intel Flexible Display Interface
Core Processor
Clock Interface
Core External pull-down
Core External pull-down
Core External pull-down
Core Clock Generator
Suspend External Pull-up
Core External Pull-up
Core External Pull-down
Core Clock Generator
®
Intel High Definition Audio Interface
SPI Interface
ASW Internal Pull-up
for details.
S0/S1 S3
High High
High High
High High
Driven Off
Driven Off
Driven Off
Driven Off
Driven Off
Low Off
Low Off
Low Off
Running Off
Driven Driven
Driven Off
Low Off
High-Z High-Z
Driven Driven
Section 1.3
S4/S5
High
High
High
Off
Off
Off
Off
Off
Off
Off
Off
Off
Driven
Off
Off
High-Z
Driven
and
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