Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 530

Bit
SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by writing
a 1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must
1 = Indicates that the SMI# was caused by:
16
SERIRQ_SMI_STS — RO.
0 = SMI# was not caused by the SERIRQ decoder.
15
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software clears this bit by writing a 1 to it.
14
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the
TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = SMI# not caused by TCO logic.
13
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake
Device Monitor Status (DEVMON_STS) — RO.
0 = SMI# not caused by Device Monitor.
12
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky,
Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0 = Indicates that there has been no access to the power management microcontroller
11
1 = Set if there has been an access to the power management microcontroller range
GPE0_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register
that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and
have the corresponding bit set in the ALT_GP_SMI_EN register. Bits that are not routed
10
to cause an SMI# will have no effect on this bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
GPE0_STS — RO. This bit is a logical OR of the bits 47:32, 14:10, 8, 6:2, and 0 in the
GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the
GPE0_EN register (PMBASE + 2Ch).
9
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register
(offset PMBASE+00h) that can cause an SMI#.
8
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
530
wait at least 15.63 s after the initial assertion of this bit before clearing it.
1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
3. The SMBus Slave receiving a Host Notify message and the
HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or
4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state.
PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the PCH generates an SMI#.
event.
so writes to this bit will have no effect.
range (62h or 66h).
(62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O
Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this
implementation assumes that the Microcontroller is on LPC. If this bit is set, and
the MCSMI_EN bit is also set, the PCH will generate an SMI#.
LPC Interface Bridge Registers (D31:F0)
Description
Datasheet