Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 33

Tables
1-1 Industry Specifications ......................................................................................... 41
1-2 Desktop Intel
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1-3 Mobile Intel
2-1 Direct Media Interface Signals ............................................................................... 55
2-2 PCI Express* Signals............................................................................................ 55
2-3 PCI Interface Signals............................................................................................ 56
2-4 Serial ATA Interface Signals .................................................................................. 58
2-5 LPC Interface Signals ........................................................................................... 61
2-6 Interrupt Signals ................................................................................................. 61
2-7 USB Interface Signals........................................................................................... 62
2-8 Power Management Interface Signals ..................................................................... 63
2-9 Processor Interface Signals ................................................................................... 67
2-10 SM Bus Interface Signals ...................................................................................... 67
2-11 System Management Interface Signals ................................................................... 68
2-12 Real Time Clock Interface ..................................................................................... 68
2-13 Miscellaneous Signals ........................................................................................... 69
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2-14 Intel High Definition Audio Link Signals................................................................. 70
2-15 Controller Link Signals.......................................................................................... 71
2-16 Serial Peripheral Interface (SPI) Signals.................................................................. 71
2-17 Thermal Signals................................................................................................... 71
2-18 Testability Signals................................................................................................ 72
2-19 Clock Interface Signals ......................................................................................... 72
2-20 LVDS Interface Signals ......................................................................................... 74
2-21 Analog Display Interface Signals ............................................................................ 75
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2-22 Intel Flexible Display Interface Signals ................................................................. 76
2-23 Digital Display Interface Signals............................................................................. 77
2-24 General Purpose I/O Signals.................................................................................. 80
2-25 Manageability Signals ........................................................................................... 84
2-26 Power and Ground Signals .................................................................................... 85
2-27 Functional Strap Definitions................................................................................... 87
3-1 Integrated Pull-Up and Pull-Down Resistors ............................................................. 93
3-2 Power Plane and States for Output and I/O Signals for Desktop Configurations ............ 95
3-3 Power Plane and States for Output and I/O Signals for Mobile Configurations ............. 101
3-4 Power Plane for Input Signals for Desktop Configurations ........................................ 107
3-5 Power Plane for Input Signals for Mobile Configurations .......................................... 110
4-1 PCH Clock Inputs ............................................................................................... 113
4-2 Clock Outputs ................................................................................................... 114
4-3 PCH PLLs .......................................................................................................... 115
4-4 SSC Blocks ....................................................................................................... 116
5-5 MSI versus PCI IRQ Actions................................................................................. 118
5-6 LAN Mode Support ............................................................................................. 125
5-7 LPC Cycle Types Supported ................................................................................. 130
5-8 Start Field Bit Definitions .................................................................................... 130
5-9 Cycle Type Bit Definitions ................................................................................... 131
5-10 Transfer Size Bit Definition.................................................................................. 131
5-11 SYNC Bit Definition ............................................................................................ 132
5-12 DMA Transfer Size ............................................................................................. 135
5-13 Address Shifting in 16-Bit I/O DMA Transfers......................................................... 136
5-14 Counter Operating Modes ................................................................................... 141
5-15 Interrupt Controller Core Connections................................................................... 143
5-16 Interrupt Status Registers................................................................................... 144
5-17 Content of Interrupt Vector Byte .......................................................................... 144
5-18 APIC Interrupt Mapping1 .................................................................................... 150
5-19 Stop Frame Explanation...................................................................................... 153
5-20 Data Frame Format ............................................................................................ 154
5-21 Configuration Bits Reset by RTCRST# Assertion ..................................................... 157
5-22 INIT# Going Active ............................................................................................ 159
5-23 NMI Sources ..................................................................................................... 160
5-24 General Power States for Systems Using the PCH ................................................... 161
5-25 State Transition Rules for the PCH........................................................................ 162
5-26 System Power Plane........................................................................................... 163
5-27 Causes of SMI and SCI ....................................................................................... 164
5-28 Sleep Types ...................................................................................................... 168
5-29 Causes of Wake Events....................................................................................... 168
5-30 GPI Wake Events ............................................................................................... 170
Datasheet
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6 Series Chipset SKUs .................................................................... 51
6 Series Chipset SKUs....................................................................... 52
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