Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 729

®
Integrated Intel High Definition Audio Controller Registers
17.1.2.39 SDLVI—Stream Descriptor Last Valid Index Register
®
(Intel
Memory Address:Input Stream[0]: HDBAR + 8Ch
Default Value:
Bit
15:8 Reserved.
Last Valid Index — R/W. The value written to this register indicates the index for the
last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it
will wrap back to the first descriptor in the list and continue processing.
7:0
This field must be at least 1; that is, there must be at least 2 valid entries in the buffer
descriptor list before DMA operations can begin.
This value should only modified when the RUN bit is 0.
17.1.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register
®
(Intel
Memory Address:Input Stream[0]: HDBAR + 8Eh
Default Value:
Bit
15:3 Reserved.
FIFO Watermark (FIFOW) — R/W. Indicates the minimum number of bytes
accumulated/free in the FIFO before the controller will start a fetch/eviction of data.
100 = 32B (Default)
101 = 64B
Others = Unsupported
2:0
NOTE: When the bit field is programmed to an unsupported size, the hardware sets
Software must read the bit field to test if the value is supported after setting the bit
field.
Datasheet
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + ACh
Input Stream[2]: HDBAR + CCh
Input Stream[3]: HDBAR + ECh
Output Stream[0]: HDBAR + 10Ch
Output Stream[1]: HDBAR + 12Ch
Output Stream[2]: HDBAR + 14Ch
Output Stream[3]: HDBAR + 16Ch
0000h
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + AEh
Input Stream[2]: HDBAR + CEh
Input Stream[3]: HDBAR + EEh
Output Stream[0]: HDBAR + 10Eh
Output Stream[1]: HDBAR + 12Eh
Output Stream[2]: HDBAR + 14Eh
Output Stream[3]: HDBAR + 16Eh
0004h
itself to the default value.
Attribute:
Size:
Description
Attribute:R/W
Size:
Description
R/W
16 bits
16 bits
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