Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 793

PCI Express* Configuration Registers
19.1.54 UES—Uncorrectable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 104h
Default Value:
This register maintains its state through a platform reset. It loses its state upon
suspend.
Bit
31:21 Reserved
Unsupported Request Error Status (URE) — R/WC. Indicates an unsupported
20
request was received.
19 ECRC Error Status (EE) — RO. ECRC is not supported.
18 Malformed TLP Status (MT) — R/WC. Indicates a malformed TLP was received.
17 Receiver Overflow Status (RO) — R/WC. Indicates a receiver overflow occurred.
Unexpected Completion Status (UC) — R/WC. Indicates an unexpected completion
16
was received.
15 Completion Abort Status (CA) — R/WC. Indicates a completer abort was received.
Completion Timeout Status (CT) — R/WC. Indicates a completion timed out. This bit
14 is set if Completion Timeout is enabled and a completion is not returned within the time
specified by the Completion TImeout Value
Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not
13
supported.
12 Poisoned TLP Status (PT) — R/WC. Indicates a poisoned TLP was received.
11:5 Reserved
Data Link Protocol Error Status (DLPE) — R/WC. Indicates a data link protocol
4
error occurred.
3:1 Reserved
0 Training Error Status (TE) — RO. Training Errors not supported.
Datasheet
107h
–
00000000000x0xxx0x0x0000000x0000b
Attribute: R/WC, RO
Size:
Description
32 bits
793