Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 253

Functional Description
The common footprint usage model is desirable during system debug and by flash
content developers since the leadless device can be easily removed and reprogrammed
without damage to device leads. When the board and flash content is mature for high-
volume production, both the socketed leadless solution and the soldered down leaded
solution are available through BOM selection.
5.24.8.2 Serial Flash Device Package Recommendations
It is highly recommended that the common footprint usage model be supported. An
example of how this can be accomplished is as follows:
• The recommended pinout for 8-pin serial flash devices is used (refer to
Section
• The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package
or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket
that is land pattern compatible with the wide body SO8 package.
• The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8
(200 mil) packages.
The 16-pin device is supported in the SO16 (300 mil) package.
5.25 Feature Capability Mechanism
A set of registers is included in the PCH LPC Interface (Device 31, Function 0, offset
E0h–EBh) that allows the system software or BIOS to easily determine the features
supported by the PCH. These registers can be accessed through LPC PCI configuration
space, thus allowing for convenient single point access mechanism for chipset feature
detection.
This set of registers consists of:
• Capability ID (FDCAP)
• Capability Length (FDLEN)
• Capability Version and Vendor-Specific Capability ID (FDVER)
• Feature Vector (FVECT)
Datasheet
5.24.7).
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