Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 896

23.5.4 PCISTS—PCI Device Status Register (IDER—D22:F2)
Address Offset: 06–07h
Default Value:
Bit
15:11
10:9
8:5
4
3
2:0
23.5.5 RID—Revision Identification Register (IDER—D22:F2)
Address Offset: 08h
Default Value:
Bit
7:0
23.5.6 CC—Class Codes Register (IDER—D22:F2)
Address Offset: 09–0Bh
Default Value:
Bit
23:16
15:8
7:0
23.5.7 CLS—Cache Line Size Register (IDER—D22:F2)
Address Offset: 0Ch
Default Value:
Bit
7:0
896
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00B0h
Reserved
DEVSEL# Timing Status (DEVT)—RO. This bit controls the device select time for
the PT function's PCI interface.
Reserved
Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer
implemented in the device.
Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the
function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when
this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host.
Reserved
See bit description
Revision ID—RO. See the Intel
of the RID Register.
010185h
Base Class Code (BCC)—RO This field indicates the base class code of the IDER
host controller device.
Sub Class Code (SCC)—RO This field indicates the sub class code of the IDER host
controller device.
Programming Interface (PI)—RO This field indicates the programming interface of
the IDER host controller device.
00h
Cache Line Size (CLS)—RO. All writes to system memory are Memory Writes.
Attribute:
Size:
Description
Attribute:
Size:
Description
®
6 Series Chipset Specification Update for the value
Attribute:
Size:
Description
Attribute:
Size:
Description
RO
16 bits
RO
8 bits
RO
24 bits
RO
8 bits
Datasheet