Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 881

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.2.4 PCISTS—PCI Status Register
(MEI—D22:F1)
Address Offset: 06h
Default Value:
Bit
15:5
4
3
2:0
23.2.5 RID—Revision Identification Register
(MEI—D22:F1)
Offset Address: 08h
Default Value:
Bit
Revision ID — RO. See the Intel
7:0
of the RID Register.
23.2.6 CC—Class Code Register
(MEI—D22:F1)
Address Offset: 09h
Default Value:
Bit
23:16
15:8
7:0
23.2.7 HTYPE—Header Type Register
(MEI—D22:F1)
Address Offset: 0Eh
Default Value:
Bit
7
6:0
Datasheet
07h
–
0010h
Reserved
Capabilities List (CL) — RO. Indicates the presence of a capabilities list, hardwired to 1.
Interrupt Status — RO. Indicates the interrupt status of the device.
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
Reserved
See bit description
0Bh
–
078000h
Base Class Code (BCC) — RO. Indicates the base class code of the Intel MEI device.
Sub Class Code (SCC) — RO. Indicates the sub class code of the Intel MEI device.
Programming Interface (PI) — RO. Indicates the programming interface of the Intel
MEI device.
80h
Multi-Function Device (MFD) — RO. Indicates the Intel MEI host controller is part of
a multifunction device.
Header Layout (HL) — RO. Indicates that the Intel MEI uses a target device layout.
Attribute:
Size:
Description
Attribute:
Size:
Description
®
6 Series Chipset Specification Update for the value
Attribute:
Size:
Description
Attribute:
Size:
Description
RO
16 bits
RO
8 bits
RO
24 bits
RO
8 bits
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