Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 750

18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 03h
Default Value:
Bit
This 8-bit field is transmitted by the host controller in the command field of the SMBus
7:0
protocol during the execution of any command.
18.2.4 XMIT_SLVA—Transmit Slave Address Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 04h
Default Value:
This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
Bit
7:1 Address — R/W. This field provides a 7-bit address of the targeted slave.
RW — R/W. Direction of the host transfer.
0
0 = Write
1 = Read
18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 05h
Default Value:
Bit
Data0/Count — R/W. This field contains the 8-bit data sent in the DATA0 field of the
SMBus protocol. For block write commands, this register reflects the number of bytes to
7:0 transfer. This register should be programmed to a value between 1 and 32 for block
counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host
controller does not check or log invalid block counts.
18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 06h
Default Value:
Bit
Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus
7:0
protocol during the execution of any command.
750
00h
00h
00h
00h
SMBus Controller Registers (D31:F3)
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
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