Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 816

21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Limit.
15:13 Reserved
Region Base (RB) / Flash Descriptor Base Address Region (FDBAR) — RO. This
specifies address bits 24:12 for the Region 0 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Base.
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register is only applicable when SPI device is in descriptor mode.
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
15:13 Reserved
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
816
SPIBAR + 54h
00000000h
Description
SPIBAR + 58h
00000000h
Description
Serial Peripheral Interface (SPI)
Attribute: RO
Size: 32 bits
Attribute: RO
Size: 32 bits
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