Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 690

17.1.1.14 SVID—Subsystem Vendor Identification Register
®
(Intel
Address Offset: 2Ch–2Dh
Default Value:
Function Level Reset: No
The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh),
enable the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3
Bit
15:0 Subsystem Vendor ID — R/WO.
17.1.1.15 SID—Subsystem Identification Register
®
(Intel
Address Offset: 2Eh–2Fh
Default Value:
Function Level Reset: No
The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch)
make it possible for the operating environment to distinguish one audio subsystem
from the other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3
T
Bit
15:0 Subsystem ID — R/WO.
17.1.1.16 CAPPTR—Capabilities Pointer Register
®
(Intel
Address Offset: 34h
Default Value:
This register indicates the offset for the capability pointer.
Bit
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability
7:0
pointer offset is offset 50h (Power Management Capability).
690
High Definition Audio Controller—D27:F0)
0000h
High Definition Audio Controller—D27:F0)
0000h
High Definition Audio Controller—D27:F0)
50h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
to D0 transition.
HOT
Description
Attribute:
Size:
to D0 transition.
HOT
Description
Attribute:
Size:
Description
R/WO
16 bits
R/WO
16 bits
RO
8 bits
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