Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 863

Thermal Sensor Registers (D31:F6)
Bit
3
2
1
0
22.2.18 TSLOCK—Thermal Sensor Register Lock Control
Offset Address: TBARB+83h
Default Value:
Bit
7:3
2
1:0
Datasheet
Auxiliary2 Low-to-High Enable — R/W.
0 = Corresponding status bit does not result in PCI interrupt.
1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal
Error Status Register.
Catastrophic Low-to-High Enable — R/W.
0 = Corresponding status bit does not result in PCI interrupt.
1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal
Error Status Register.
Hot Low-to-High Enable— R/W.
0 = Corresponding status bit does not result in PCI interrupt.
1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal
Error Status Register.
Auxiliary Low-to-High Enable — R/W.
0 = Corresponding status bit does not result in PCI interrupt.
1 = PCI interrupt is signaled when the corresponding status bit is set in the Thermal
Error Status Register.
00h
Reserved
Lock Control — R/W. This bit can only be set to a 0 by a host-partitioned reset.
Writing a 0 to this bit has no effect.
NOTE: CF9 warm reset is a host-partitioned reset.
Reserved
Description
Attribute: R/W
Size: 8 bit
Description
863