Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 635

SATA Controller Registers (D31:F5)
15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)
Address Offset: Primary: BAR + 02h
Default Value:
Bit
PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
7
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit
6 Reserved.
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
5
4:3 Reserved.
Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
2
1 = Set when a device FIS is received with the 'I' bit set, provided that software has not
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1
1 = This bit is set when the controller encounters a target abort or master abort when
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the PCH when the last transfer for a region is performed,
0
1 = Set by the PCH when the Start bit is written to the Command register.
15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5)
Address Offset: Primary: BAR + 04h–07h
Default Value:
Bit
31:2
1:0
Datasheet
Secondary: BAR + 0Ah
00h
set.
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The PCH does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
disabled interrupts using the IEN bit of the Device Control Register (see chapter 5
of the Serial ATA Specification, Revision 1.0a).
transferring data on PCI.
where EOT for that region is set in the region descriptor. It is also cleared by the
PCH when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
Secondary: BAR + 0Ch
All bits undefined
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
Reserved
Attribute: R/W, R/WC, RO
Size: 8 bits
Description
Attribute: R/W
0Fh
–
Size: 32 bits
Description
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