Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 666

Bit
Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by
software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller
6
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is
Asynchronous Schedule Enable — R/W. This bit controls whether the host controller
skips processing the Asynchronous Schedule.
5
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Periodic Schedule Enable — R/W. This bit controls whether the host controller skips
processing the Periodic Schedule.
4
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
Frame List Size — RO. The PCH hardwires this field to 00b because it only supports
3:2
the 1024-element frame list size.
Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset
the host controller. The effects of this on root hub registers are similar to a Chip
Hardware Reset (that is, RSMRST# assertion and PWROK deassertion on the PCH).
When software writes a 1 to this bit, the host controller resets its internal pipelines,
timers, counters, state machines, etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated. A USB reset is not driven on downstream
ports.
NOTE: PCI configuration registers and Host controller capability registers are not
1
All operational registers, including port registers and port state machines are set to
their initial values. Port ownership reverts to the companion host controller(s), with the
side effects described in the EHCI specification. Software must re-initialize the host
controller in order to return the host controller to an operational state.
This bit is set to 0 by the host controller when the reset process is complete. Software
cannot terminate the reset process early by writing a 0 to this register.
Software should not set this bit to a 1 when the HCHalted bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to
reset an actively running host controller will result in undefined behavior. This reset me
be used to leave EHCI port test modes.
666
Advance status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS
register to a 1.
has evicted all appropriate cached schedule state, it sets the Interrupt on Async
Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance
Enable bit in the USB2.0_INTR register (D29:F0, D26:F0:CAPLENGTH + 28h, bit 5)
is a 1 then the host controller will assert an interrupt at the next interrupt
threshold. See the EHCI specification for operational details.
inactive. Doing so will yield undefined results.
effected by this reset.
EHCI Controller Registers (D29:F0, D26:F0)
Description
Datasheet