Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 800

Table 20-1. Memory-Mapped Registers (Sheet 2 of 2)
Offset
130–13Fh
140–147h
148–14Fh
150–15Fh
160–167h
168–16Fh
180–187h
188–18Fh
190–19Fh
1A0–1A7h
1A8–1AFh
1B0–1BFh
1C0–1C7h
1C8–1CFh
1D0–1DFh
1E0–1E7h
1E8–1EFh
1F0–19Fh
200–3FFh
NOTES:
1. Reads to reserved registers or bits will return a value of 0.
2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision
Event Timers. If attempted, the lock is not honored, which means potential deadlock
conditions may occur.
800
Mnemonic
— Reserved
TIM2_CONF Timer 2 Configuration and Capabilities
TIM2_COMP Timer 2 Comparator Value
— Reserved
TIM3_CONG Timer 3 Configuration and Capabilities
TIM3_COMP Timer 3 Comparator Value
TIM4_CONG Timer 4 Configuration and Capabilities
TIM4_COMP Timer 4 Comparator Value
— Reserved
TIM5_CONG Timer 5 Configuration and Capabilities
TIM5_COMP Timer 5 Comparator Value
— Reserved
TIM6_CONG Timer 6 Configuration and Capabilities
TIM6_COMP Timer 6 Comparator Value
— Reserved
TIM7_CONG Timer 7 Configuration and Capabilities
TIM7_COMP Timer 7 Comparator Value
— Reserved
— Reserved
High Precision Event Timer Registers
Register Default Type
— —
N/A R/W, RO
N/A R/W
— —
N/A R/W, RO
N/A R/W
N/A R/W, RO
N/A R/W
— —
N/A R/W, RO
N/A R/W
— —
N/A R/W, RO
N/A R/W
— —
N/A R/W, RO
N/A R/W
— —
— —
Datasheet