Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 780

19.1.33 SLSTS—Slot Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 5Ah
Default Value:
Bit
15:9 Reserved
Link Active State Changed (LASC) — R/WC.
1 = This bit is set when the value reported in Data Link Layer Link Active field of the
8
7 Reserved
Presence Detect State (PDS) — RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5/F6/
F7:42h:bit 8) is set (indicating that this root port spawns a slot), then this bit:
6 0 = Indicates the slot is empty.
1 = Indicates the slot has a device connected.
Otherwise, if XCAP.SI is cleared, this bit is always set (1).
5 MRL Sensor State (MS) — Reserved as the MRL sensor is not implemented.
4 Reserved
Presence Detect Changed (PDC) — R/WC.
3
0 = No change in the PDS bit.
1 = The PDS bit changed states.
2 MRL Sensor Changed (MSC) — Reserved as the MRL sensor is not implemented.
1 Power Fault Detected (PFD) — Reserved as a power controller is not implemented.
0 Reserved
780
5Bh
–
0000h
Link Status register (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed. In
response to a Data Link Layer State Changed event, software must read Data Link
Layer Link Active field of the Link Status register to determine if the link is active
before initiating configuration cycles to the hot plugged device.
PCI Express* Configuration Registers
Attribute: R/WC, RO
Size: 16 bits
Description
Datasheet